Joshua Fryman, Intel Fellow, received his Ph.D. from Georgia Institute of Technology, and B.S. degree from University of Florida. Prior to joining Intel Corporation in 2005, Joshua worked on cable and satellite systems. From 2005-2012, he was with the Intel Labs aside from a brief tour from 2009-2010 in the Software Solutions Group working on virtual ISA and support for what became Xeon Phi. Since 2012, he has led a vertically integrated applied R&D team as part of Intel's Office of the CTO with Datacenter Technologies (2012-2020) and Intel's Office of the CTO (2020-present).

His research activities include novel microprocessor architecture, co-design of workloads and systems, disaggregated system architecture, high-performance computing, embedded systems, novel memory architectures, photonic chip networks, and at-scale system fabrics. He has been lead architect or PI for multiple advanced research programs from DARPA, IARPA, DOE, and commercial entities since 2010. He has multiple public peer-reviewed publications, holds many granted patents, solely authored one book on the Intel Larrabee architecture that shipped with every unit delivered, and supports multiple STEAM activities and diversity programs.